Nowadays, many electrical appliances are widely used with computers due to the amazing power of computers. For example, video compact disks (VCDs) and digital versatile disks (DVDs) are able to be played by a personal computer. Since the size of a typical computer monitor is not large enough to exhibit the spectacular video effect of the VCD or DVD disks, it is preferred that the signals be outputted from the personal computer to a TV set to be displayed on the relatively large TV screen. The purpose can be achieved by employing a display adapter.
FIG. 1(a) is a partial functional block diagram of a typical display adapter. The pixel parallel digital signals from a graphic chip 10 are selectively converted into a proper format of analog signals via either a random access memory digital-to-analog converter (RAM DAC) 11 or a TV encoder 12, and delivered to a computer monitor 13 or a TV screen 14, respectively, for display. Further, for TV analog signals, two formats, i.e. the NTSC (National Television Standards Committee) standard and the PAL (Phase Alternate Line) standard, are involved.
The functional block diagram of the TV encoder 12 can be seen in FIG. 1(b). The pixel parallel digital signals from the graphic chip 10 is processed by a data capture device 121, a color space converter 122, a scalar and deflicker 123, an NTSC/PAL encoder 124 and a digital-to-analog converter 125 to produce the TV analog signals either in the NTSC or PAL standard. The pixel clock required to operate the NTSC/PAL encoder 124 is produced from a phase-locked loop clock generator 126. In order to synchronize the pixel clock with the system clock required to operate the graphic chip 10, the pixel clock is generated in response to the system clock. In such way, a possible frequency drift of the system clock will also result in a frequency drift of the pixel clock. In general, the system clock for operating the graphic chip 10 permits a larger tolerance than the pixel clock. If the acceptable frequency drift of the system clock results in the corresponding frequency drift of the pixel clock, rendering a frequency error beyond the tolerance of the pixel clock, the output TV analog signal from the NTSC/PAL encoder 124 cannot be correctly decoded, and thus no normal picture is shown on the TV screen.
In order to overcome the above-described problem, a clock generator is provided in the NTSC/PAL encoder 124 to compensate the frequency drift effect of the pixel clock, as disclosed in U.S. Pat. No. 5,874,846, which is incorporated herein for reference. Please refer to FIG. 2 which is a circuit block diagram schematically showing the clock generator. The clock generator 300 includes a clock measuring circuit 310 and a P:Q ratio counter 311. The clock measuring circuit 310 operates to output a measuring value Nr, which is provided for the P:Q ratio counter 311 with the original pixel clock of a frequency Fs. The P:Q ratio counter 311 operates to generate the desired compensated pixel clock of a frequency Fo accordingly. The measuring value Nr outputted from the clock measuring circuit 310 is given by:Nr=Ns×Fr/Fswhere Ns is a predetermined counting value, Fs is the frequency of the original pixel clock, and Fr is the frequency of the clock generated by an oscillator inside the TV encoder 12, and wherein Fr is inherently much more accurate than Fs.
The P:Q ratio counter 311 is triggered by the input of the measuring value Nr and the original pixel clock to generate an output clock signal of the frequency Fo, which complies with the demand of the NTSC/PAL encoder 124. The output clock frequency Fo correlates to the original pixel clock frequency Fs by the following equation:Fo=(P/Q)×Fswhere Q is a constant parameter and P=Nr.
In such way, the introduction of the measuring value Nr that varies with the original pixel clock frequency Fs enables a more stable output of the clock frequency Fo from the P:Q ratio counter that is also triggered by the original pixel clock. Since the output clock frequency Fo has stablized, the output TV analog signals from the NTSC/PAL encoder 124 can be correctly decoded. However, the circuit configuration of the above clock generator 300 has some disadvantages. For example, the system 3101 and the reference counter 3013 included in the clock measuring circuit 310 have a phase difference due to the operation of a synchronizing controller 3012 disposed therebetween. The phase difference is generally ranged from 0.5 Tr to 1.0 Tr, where Tr=1/Fr, which adversely effects the stability of the output clock frequency Fo.